Asynchronous Network-on-Chip Overview
The Problem: Chip Complexity at 7 Billion Transistors and Growing
Integrated circuit density continues to increase according to Moore's Law, with record-breaking ICs today containing 7-billion transistors in a single package. Designers of such a System-on-a-Chip (SoC) face extremely complex problems in meeting global timing and power constraints, particularly when multiple clock domains are required. With large chips costing tens of millions of dollars and taking upwards of 18 months to design, the cost to companies of “getting it wrong” can be catastrophic.
Approach: Asynchronous Network-on-Chip
Blendics tools support multi-synchronous design techniques that create an asynchronous network-on-chip (ANoC) -- an error-free global interconnection network -- allowing engineers to easily create modular, hierarchical designs for today’s denser chips. Features of the Blendics approach include:
- Reliable global timing. The ANoC created by Blendics tools ensures that global timing is correct, regardless of a core’s position on the chip.
- Multiple clock domains supported. Because existing synchronous cores of different speeds are allowed to coexist on the same SoC, reuse is increased and clock domain crossing (CDC) design is simplified.
- Works with existing tools. The Blendics toolset works with standard EDA design tools, including timing analysis tools; preserving existing tool flows.
- Flexible place and route. The asynchronous on-chip network simplifies design, supports flexible place and route, and utilizes standard design constraints (SDCs).
- Reduced time-to-market. By eliminating costly design iterations often needed to achieve timing closure, Blendics tools dramatically reduce time-to-market.
- Reduced power and increased reliability. The integration of a product into an SoC can substantially reduce power requirements by eliminating many off-chip signal paths and by stopping clocks in idle subsystems. Furthermore, a product with fewer parts has fewer ways to fail.
- Reduced NRE costs. The minimization of engineering time and the reuse of IP cores make possible the integration of products that would not ordinarily fit within the budget constraints associated with low production.
Blendics’ ability to reduce cost and time-to-market, while simultaneously increasing reliability and performance, makes the ANoC approach attractive in many markets that utilize high-performance or low-power SoCs.
The following applications represent a sample of those that have a critical need for the benefits provided by Blendics’ technology:
- FPGA Hardware-Accelerated Appliances for Financial Services
- Telecommunications (Cellular Base Station Line Cards)
- Mobile SoCs