You are here: HomeCompanyNewsBlendics Receives SBIR Phase I Funding

The company's approach blends clock-free and clocked design paradigms thereby retaining the advantages of conventional tools while avoiding their disadvantages. The intended project outcomes are:

  • The design of a family of Delay-tolerant, Asynchronous Interfaces (DANI), which can be assembled into a wrapper for traditionally designed, clocked-components
  • Creation of an automatic wrapper generator that will allow the wrapped components to appear to their neighbors as if they were clock-free
  • Validation that the wrapper generator functions properly on a set of components randomly chosen from a popular silicon-IP website.

This is a critical step iin the creation of a new class of SoC design tools that fit well with existing tools, but make possible relative timing between components instead of the current, but fragile synchronous timing between components. By adopting this new class of SoC design tools, the IC designer saves significant design time and overall project cost.

 

 

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