To get a handle on the answer, the study group worked out a fairly detailed supercomputer design. They picked 0.5V supply voltage to overcome the power consumption problems. Kogge says they picked that voltage "because it represents the best projection for what industry-standard silicon-based logic circuitry would be able to offer by 2015." He notes that this reduces power, "but you also reduce the speed of the chip and make circuits more prone to transient malfunctions."
Kogge also says, "As if the problems we had with excessive power draw and memory inadequacies weren't enough, the panel also found that lowering the operating voltage, as we presumed was necessary, would make the transistors prone to new and more frequent faults, especially temperature-induced transient glitches. When you add this tendency to the very large number of components projected -- you have to worry about the resiliency of such systems."
Kogge is describing just the problems that MetaACE, ClosureACE and DANI wrappers are designed to address: transient glitches due to synchronizer metastability faults and interconnect delay variations. These problems will not only plaque supercomputer desgins but also all low-power SoC designs at process nodes of 40 nm and below.