Created on Tuesday, 26 June 2012 00:27
On June 26, 2012, Blendics was awarded $499,862 in supplemental Phase IIB funding from the National Science Foundation. This follows prior funding through NSF's Small Business Technology Transfer program. This grant will support continued research and testing of the Blendics tools. These tools support multi-synchronous design techniques that create an asynchronous network-on-chip (ANoC).
The benefits of this approach are:
The bottom line is that a reduction in engineering time by up to half is possible with the Blendics flow.
Created on Thursday, 07 June 2012 22:26
On Monday June 4th, Blendics moved to a wonderful new home at 10176 Corporate Square Drive, Suite 200, St. Louis, Missouri 63132. We are thrilled to have more office space, meeting space and a larger lab. The new offices are centrally located in the St. Louis County suburb of Creve Coeur, near Lindbergh Blvd. and Olive Blvd. We are still convenient to major highways and the airport. The company phone number remains the same - 314-738-0403.
Created on Friday, 09 September 2011 16:50
St. Louis-based Blendics, Inc., a provider of design tools, design services and semiconductor intellectual property (IP) for advanced system-on-chip (SoC) designs, today announced the close of a first round of funding totaling $1M from National Innovation Fund. National Innovation Fund is an Omaha-based early-stage venture firm. Blendics will use the capital to advance its Asynchronous Network on Chip (ANoC) product portfolio and to expand its market presence in the $5 billion electronic design automation (EDA) and the $1.7 billion silicon intellectual property industries.Read more: Blendics Secures $1M Series A to Commercialize Asynchronous System-on-Chip Networking Technology
Created on Wednesday, 16 November 2011 19:45
On November 16, 2011, the National Science Foundation awarded an SBIR (Small Business Innovation Research) Phase I grant to Blendics.
This grant supported Blendics' development of a wrapper technology. This technology makes each SoC subsystem appear as if it were clock-free (asynchronous) and independent of its neighbors, thereby reducing the undesirable effects of transistor variability and enabling power reduction techniques. The goal of the research is to automate this design task, making widespread use of these wrappers more economical.Read more: Blendics Receives SBIR Phase I Funding
Created on Friday, 07 January 2011 11:00
Blendics received supplemental funding under the National Science Foundation's Technology Enhancement Commercial Partnerships (TECP) program to support collaborations with Xilinx, Inc., of San Jose, California and with Exegy, Inc., of St. Louis, Missouri.
This funding will facilitate research ultimately proving that the Blendics' tools will allow Exegy to be more responsive to customer demands. The research will also assist Xilinx in resolving difficult timing closure problems, an increasingly common problem at 45 nm and below.Read more: Blendics Receives National Science Foundation TECP Award to Support High Performance ANoC Technology