DANI (Delay-tolerant Asynchronous Network Interface) wrappers provide an interface between the traditionally designed, multi-synchronous core and the global asynchronous network-on-chip.
DANI wrappers are delivered as silicon IP, ready to be incorporated into System-on-Chip designs.
DANI wrappers feature:
- A light-weight, low-latency asynchronous FIFO based on a proprietary Blendics design
- Token-based word-by-word flow control with multiple words-in-flight
- No speed penalty over traditional synchronous designs
- Support for dynamic clock frequency scaling, which can reduce chip power requirements